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MSMON_CSA

MSMON_CSA, MPAM Cache Storage Allocation Monitor Register

The MSMON_CSA characteristics are:

Purpose

Accesses the cache storage allocation monitor instance selected by MSMON_CFG_MON_SEL.

Configuration

The power domain of MSMON_CSA is IMPLEMENTATION DEFINED.

This register is present only when FEAT_MPAM_CSA is implemented. Otherwise, direct accesses to MSMON_CSA are RES0.

If MPAMF_IDR.HAS_RIS is 1, the monitor instance register accessed is for the resource instance currently selected by MSMON_CFG_MON_SEL.RIS and the monitor instance of that resource instance selected by MSMON_CFG_MON_SEL.MON_SEL.

If FEAT_MPAMv0p1 or FEAT_MPAMv1p0 is implemented, the register is banked and the following statements apply:

MSMON_CSA_s is the Secure cache storage allocation monitor instance selected by the Secure instance of MSMON_CFG_MON_SEL.
MSMON_CSA_ns is the Non-secure cache storage allocation monitor instance selected by the Non-secure instance of MSMON_CFG_MON_SEL.
If FEAT_RME is implemented, the following statements also apply:
- MSMON_CSA_rt is the Root cache storage allocation monitor instance selected by the Root instance of MSMON_CFG_MON_SEL.
- MSMON_CSA_rl is the Realm cache storage allocation monitor instance selected by the Realm instance of MSMON_CFG_MON_SEL.

The power and reset domain of each MSC component is specific to that component.

Attributes

MSMON_CSA is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NRDY	VALUE

NRDY, bit [31]

Not Ready. Indicates whether the monitor has possibly inaccurate data.

NRDY	Meaning
0b0	The monitor instance is ready and the MSMON_CSA.VALUE field is accurate.
0b1	The monitor instance is not ready and the contents of the MSMON_CSA.VALUE field might be inaccurate or otherwise not represent the actual cache storage allocations.

VALUE, bits [30:0]

Cache storage allocation counter value if MSMON_CSA.NRDY is 0. Invalid if MSMON_CSA.NRDY is 1.

VALUE is the scaled count of bytes allocated since the monitor was last reset that met the criteria set in MSMON_CFG_CSA_FLT and MSMON_CFG_CSA_CTL for the monitor instance selected by MSMON_CFG_MON_SEL.

If MSMON_CFG_CSA_CTL.SCLEN enables scaling, the count in VALUE is the number of bytes shifted right by MPAMF_CSAMON_IDR.SCALE bit positions and rounded.

Accessing MSMON_CSA

This register is within the MPAM feature page memory frames.

If FEAT_MPAM is implemented, the following statements apply:

In a system that supports Secure and Non-secure memory maps, there must be both Secure and Non-secure MPAM feature pages.
MSMON_CSA_s must only be accessible from the Secure MPAM feature page. MSMON_CSA_ns must only be accessible from the Non-secure MPAM feature page.
MSMON_CSA_s and MSMON_CSA_ns must be separate registers. The Secure instance (MSMON_CSA_s) accesses the cache storage allocation monitor used for Secure PARTIDs, and the Non-secure instance (MSMON_CSA_ns) accesses the cache storage allocation monitor used for Non-secure PARTIDs.

If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply:

In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:
MSMON_CSA_s must only be accessible from the Secure MPAM feature page.
MSMON_CSA_ns must only be accessible from the Non-secure MPAM feature page.
MSMON_CSA_rt must only be accessible from the Root MPAM feature page.
MSMON_CSA_rl must only be accessible from the Realm MPAM feature page.
MSMON_CSA_s, MSMON_CSA_ns, MSMON_CSA_rt, and MSMON_CSA_rl must be separate registers:
The Secure instance (MSMON_CSA_s) accesses the cache storage allocation monitor used for Secure PARTIDs.
The Non-secure instance (MSMON_CSA_ns) accesses the cache storage allocation monitor used for Non-secure PARTIDs.
The Root instance (MSMON_CSA_rt) accesses the cache storage allocation monitor used for Root PARTIDs.
The Realm instance (MSMON_CSA_rl) accesses the cache storage allocation monitor used for Realm PARTIDs.

If any one of these features is implemented:

FEAT_MPAMv0p1
FEAT_MPAMv1p1

then, the following statements apply:

When RIS is implemented, reads and writes to MSMON_CSA access the cache storage allocation monitor instance for the resource instance selected by MSMON_CFG_MON_SEL.RIS and the cache storage allocation monitor instance selected by MSMON_CFG_MON_SEL.MON_SEL.
When RIS is not implemented, reads and writes to MSMON_CSA access the cache storage allocation monitor instance for the cache storage allocation monitor instance selected by MSMON_CFG_MON_SEL.MON_SEL.

Otherwise, the following statements apply:

Reads and writes to MSMON_CSA access the cache storage allocation monitor for the cache storage allocation monitor instance selected by MSMON_CFG_MON_SEL.MON_SEL.

MSMON_CSA can be accessed through the memory-mapped interfaces:

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_s	0x08A0	MSMON_CSA_s

When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented, accesses to this register are RW.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_ns	0x08A0	MSMON_CSA_ns

When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented, accesses to this register are RW.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_rt	0x08A0	MSMON_CSA_rt

When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented), accesses to this register are RW.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_rl	0x08A0	MSMON_CSA_rl

When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented), accesses to this register are RW.

2026-03-26 20:27:25, 2026-03_rel