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MSMON_CSU

MSMON_CSU, MPAM Cache Storage Usage Monitor Register

The MSMON_CSU characteristics are:

Purpose

Accesses the CSU monitor instance selected by MSMON_CFG_MON_SEL.

Configuration

The power domain of MSMON_CSU is IMPLEMENTATION DEFINED.

This register is present only when FEAT_MPAM_MSC_MSMON is implemented and MPAMF_MSMON_IDR.MSMON_CSU == '1'. Otherwise, direct accesses to MSMON_CSU are RES0.

If MPAMF_IDR.HAS_RIS is 1, the monitor instance register accessed is for the resource instance currently selected by MSMON_CFG_MON_SEL.RIS and the monitor instance of that resource instance selected by MSMON_CFG_MON_SEL.MON_SEL.

If FEAT_MPAMv0p1 or FEAT_MPAMv1p0 is implemented, the register is banked and the following statements apply:

MSMON_CSU_s is the Secure cache storage usage monitor instance selected by the Secure instance of MSMON_CFG_MON_SEL.
MSMON_CSU_ns is the Non-secure cache storage usage monitor instance selected by the Non-secure instance of MSMON_CFG_MON_SEL.
If FEAT_RME is implemented, the following statements also apply:
- MSMON_CSU_rt is the Root cache storage usage monitor instance selected by the Root instance of MSMON_CFG_MON_SEL.
- MSMON_CSU_rl is the Realm cache storage usage monitor instance selected by the Realm instance of MSMON_CFG_MON_SEL.

The power and reset domain of each MSC component is specific to that component.

Attributes

MSMON_CSU is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NRDY	VALUE

NRDY, bit [31]

Not Ready. Indicates whether the monitor instance has possibly inaccurate data.

NRDY	Meaning
0b0	The monitor instance is ready and the MSMON_CSU.VALUE field is accurate.
0b1	The monitor instance is not ready and the contents of the MSMON_CSU.VALUE field might be inaccurate or otherwise not represent the actual cache storage usage.

VALUE, bits [30:0]

Cache storage usage measurement value if MSMON_CSU.NRDY is 0. Invalid if MSMON_CSU.NRDY is 1.

VALUE is the cache storage usage measured in bytes meeting the criteria set in MSMON_CFG_CSU_FLT and MSMON_CFG_CSU_CTL for the monitor instance selected by MSMON_CFG_MON_SEL.

Accessing MSMON_CSU

If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply:

In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:
MSMON_CSU_s must only be accessible from the Secure MPAM feature page.
MSMON_CSU_ns must only be accessible from the Non-secure MPAM feature page.
MSMON_CSU_rt must only be accessible from the Root MPAM feature page.
MSMON_CSU_rl must only be accessible from the Realm MPAM feature page.
MSMON_CSU_s, MSMON_CSU_ns, MSMON_CSU_rt, and MSMON_CSU_rl must be separate registers:
The Secure instance (MSMON_CSU_s) accesses the cache storage usage monitor used for Secure PARTIDs.
The Non-secure instance (MSMON_CSU_ns) accesses the cache storage usage monitor used for Non-secure PARTIDs.
The Root instance (MSMON_CSU_rt) accesses the cache storage usage monitor used for Root PARTIDs.
The Realm instance (MSMON_CSU_rl) accesses the cache storage usage monitor used for Realm PARTIDs.

If any one of these features is implemented:

FEAT_MPAMv0p1
FEAT_MPAMv1p1

then, the following statements apply:

When RIS is implemented, reads and writes to MSMON_CSU access the cache storage usage monitor monitor instance for the cache resource instance selected by MSMON_CFG_MON_SEL.RIS and the cache storage usage monitor instance selected by MSMON_CFG_MON_SEL.MON_SEL.
When RIS is not implemented, reads and writes to MSMON_CSU access the cache storage usage monitor monitor instance for the cache storage usage monitor instance selected by MSMON_CFG_MON_SEL.MON_SEL.

Otherwise, the following statements apply:

Reads and writes to MSMON_CSU access the cache storage usage monitor monitor for the cache storage usage monitor instance selected by MSMON_CFG_MON_SEL.MON_SEL.

MSMON_CSU can be accessed through the memory-mapped interfaces:

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_s	0x0840	MSMON_CSU_s

Accessible as follows:

When (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) and MPAMF_CSUMON_IDR.CSU_RO == '0', accesses to this register are RW.
When (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) and MPAMF_CSUMON_IDR.CSU_RO == '1', accesses to this register are RO.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_ns	0x0840	MSMON_CSU_ns

Accessible as follows:

When (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) and MPAMF_CSUMON_IDR.CSU_RO == '0', accesses to this register are RW.
When (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented) and MPAMF_CSUMON_IDR.CSU_RO == '1', accesses to this register are RO.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_rt	0x0840	MSMON_CSU_rt

Accessible as follows:

When FEAT_RME is implemented, (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented), and MPAMF_CSUMON_IDR.CSU_RO == '0', accesses to this register are RW.
When FEAT_RME is implemented, (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented), and MPAMF_CSUMON_IDR.CSU_RO == '1', accesses to this register are RO.

Component	Frame	Offset	Instance
MPAM	MPAMF_BASE_rl	0x0840	MSMON_CSU_rl

Accessible as follows:

When FEAT_RME is implemented, (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented), and MPAMF_CSUMON_IDR.CSU_RO == '0', accesses to this register are RW.
When FEAT_RME is implemented, (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented), and MPAMF_CSUMON_IDR.CSU_RO == '1', accesses to this register are RO.

2026-03-26 20:27:25, 2026-03_rel