HFGRTR2

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HFGRTR2_EL2, Hypervisor Fine-Grained Read Trap Register 2

Purpose

Configuration

This register is present only when FEAT_FGT2 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to HFGRTR2_EL2 are UNDEFINED.

Attributes

Field descriptions

Bits [63:40]

ACTLR_EL1, bit [39]
When FEAT_SRMASK is implemented:

Trap MRS reads of ACTLR_EL1 at EL1 using AArch64 to EL2.

ACTLR_EL1	Meaning
0b0	MRS reads of ACTLR_EL1 are not trapped by this mechanism.
0b1	If EL2 is implemented and enabled in the current Security state, then MRS reads of ACTLR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [38:15]

nACTLRALIAS_EL1, bit [14]
When FEAT_SRMASK is implemented:

Trap MRS reads of ACTLRALIAS_EL1 at EL1 using AArch64 to EL2.

nACTLRALIAS_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of ACTLRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of ACTLRALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nACTLRMASK_EL1, bit [13]
When FEAT_SRMASK is implemented:

Trap MRS reads of ACTLRMASK_EL1 at EL1 using AArch64 to EL2.

nACTLRMASK_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of ACTLRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of ACTLRMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nTCR2ALIAS_EL1, bit [12]
When FEAT_SRMASK is implemented:

Trap MRS reads of TCR2ALIAS_EL1 at EL1 using AArch64 to EL2.

nTCR2ALIAS_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of TCR2ALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of TCR2ALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nTCRALIAS_EL1, bit [11]
When FEAT_SRMASK is implemented:

Trap MRS reads of TCRALIAS_EL1 at EL1 using AArch64 to EL2.

nTCRALIAS_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of TCRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of TCRALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSCTLR2ALIAS_EL1, bit [10]
When FEAT_SRMASK is implemented:

Trap MRS reads of SCTLR2ALIAS_EL1 at EL1 using AArch64 to EL2.

nSCTLR2ALIAS_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of SCTLR2ALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of SCTLR2ALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSCTLRALIAS_EL1, bit [9]
When FEAT_SRMASK is implemented:

Trap MRS reads of SCTLRALIAS_EL1 at EL1 using AArch64 to EL2.

nSCTLRALIAS_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of SCTLRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of SCTLRALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nCPACRALIAS_EL1, bit [8]
When FEAT_SRMASK is implemented:

Trap MRS reads of CPACRALIAS_EL1 at EL1 using AArch64 to EL2.

nCPACRALIAS_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of CPACRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of CPACRALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nTCR2MASK_EL1, bit [7]
When FEAT_SRMASK is implemented:

Trap MRS reads of TCR2MASK_EL1 at EL1 using AArch64 to EL2.

nTCR2MASK_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of TCR2MASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of TCR2MASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nTCRMASK_EL1, bit [6]
When FEAT_SRMASK is implemented:

Trap MRS reads of TCRMASK_EL1 at EL1 using AArch64 to EL2.

nTCRMASK_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of TCRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of TCRMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSCTLR2MASK_EL1, bit [5]
When FEAT_SRMASK is implemented:

Trap MRS reads of SCTLR2MASK_EL1 at EL1 using AArch64 to EL2.

nSCTLR2MASK_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of SCTLR2MASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of SCTLR2MASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nSCTLRMASK_EL1, bit [4]
When FEAT_SRMASK is implemented:

Trap MRS reads of SCTLRMASK_EL1 at EL1 using AArch64 to EL2.

nSCTLRMASK_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of SCTLRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of SCTLRMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nCPACRMASK_EL1, bit [3]
When FEAT_SRMASK is implemented:

Trap MRS reads of CPACRMASK_EL1 at EL1 using AArch64 to EL2.

nCPACRMASK_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of CPACRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of CPACRMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nRCWSMASK_EL1, bit [2]
When FEAT_THE is implemented:

Trap MRS or MRRS reads of RCWSMASK_EL1 at EL1 using AArch64 to EL2.

nRCWSMASK_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then unless the read generates a higher priority exception: MRS reads of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRRS reads of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14.
0b1	MRS and MRRS reads of RCWSMASK_EL1 are not trapped by this mechanism.

nRCWSMASK_EL1

Meaning

0b0

If EL2 is implemented and enabled in the current Security state, then unless the read generates a higher priority exception:

MRS reads of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
MRRS reads of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14.

0b1

MRS and MRRS reads of RCWSMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nERXGSR_EL1, bit [1]
When FEAT_RASv2 is implemented:

Trap MRS reads of ERXGSR_EL1 at EL1 using AArch64 to EL2.

nERXGSR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of ERXGSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of ERXGSR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

Accessing this field has the following behavior:

This field is permitted to be RES0 if all of the following are true:
- ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI.
- ERRIDR_EL1.NUM is zero.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

nPFAR_EL1, bit [0]
When FEAT_PFAR is implemented:

Trap MRS reads of PFAR_EL1 at EL1 using AArch64 to EL2.

nPFAR_EL1	Meaning
0b0	If EL2 is implemented and enabled in the current Security state, then MRS reads of PFAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception.
0b1	MRS reads of PFAR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

EL3 is implemented.
SCR_EL3.FGTEn2 == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to '0'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

Accessing HFGRTR2_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HFGRTR2_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0011	0b0001	0b010

if !(IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x2C0); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn2 == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HFGRTR2_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HFGRTR2_EL2(); end;

MSR HFGRTR2_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0011	0b0001	0b010

if !(IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x2C0) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn2 == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HFGRTR2_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HFGRTR2_EL2() = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								ACTLR_EL1	RES0
RES0																	nACTLRALIAS_EL1	nACTLRMASK_EL1	nTCR2ALIAS_EL1	nTCRALIAS_EL1	nSCTLR2ALIAS_EL1	nSCTLRALIAS_EL1	nCPACRALIAS_EL1	nTCR2MASK_EL1	nTCRMASK_EL1	nSCTLR2MASK_EL1	nSCTLRMASK_EL1	nCPACRMASK_EL1	nRCWSMASK_EL1	nERXGSR_EL1	nPFAR_EL1

HFGRTR2_EL2, Hypervisor Fine-Grained Read Trap Register 2

Purpose

Configuration

Attributes

Field descriptions

Bits [63:40]

ACTLR_EL1, bit [39]When FEAT_SRMASK is implemented:

Otherwise:

Bits [38:15]

nACTLRALIAS_EL1, bit [14]When FEAT_SRMASK is implemented:

Otherwise:

nACTLRMASK_EL1, bit [13]When FEAT_SRMASK is implemented:

Otherwise:

nTCR2ALIAS_EL1, bit [12]When FEAT_SRMASK is implemented:

Otherwise:

nTCRALIAS_EL1, bit [11]When FEAT_SRMASK is implemented:

Otherwise:

nSCTLR2ALIAS_EL1, bit [10]When FEAT_SRMASK is implemented:

Otherwise:

nSCTLRALIAS_EL1, bit [9]When FEAT_SRMASK is implemented:

Otherwise:

nCPACRALIAS_EL1, bit [8]When FEAT_SRMASK is implemented:

Otherwise:

nTCR2MASK_EL1, bit [7]When FEAT_SRMASK is implemented:

Otherwise:

nTCRMASK_EL1, bit [6]When FEAT_SRMASK is implemented:

Otherwise:

nSCTLR2MASK_EL1, bit [5]When FEAT_SRMASK is implemented:

Otherwise:

nSCTLRMASK_EL1, bit [4]When FEAT_SRMASK is implemented:

Otherwise:

nCPACRMASK_EL1, bit [3]When FEAT_SRMASK is implemented:

Otherwise:

nRCWSMASK_EL1, bit [2]When FEAT_THE is implemented:

Otherwise:

nERXGSR_EL1, bit [1]When FEAT_RASv2 is implemented:

Otherwise:

nPFAR_EL1, bit [0]When FEAT_PFAR is implemented:

Otherwise:

Accessing HFGRTR2_EL2

MRS <Xt>, HFGRTR2_EL2

MSR HFGRTR2_EL2, <Xt>

ACTLR_EL1, bit [39]
When FEAT_SRMASK is implemented:

nACTLRALIAS_EL1, bit [14]
When FEAT_SRMASK is implemented:

nACTLRMASK_EL1, bit [13]
When FEAT_SRMASK is implemented:

nTCR2ALIAS_EL1, bit [12]
When FEAT_SRMASK is implemented:

nTCRALIAS_EL1, bit [11]
When FEAT_SRMASK is implemented:

nSCTLR2ALIAS_EL1, bit [10]
When FEAT_SRMASK is implemented:

nSCTLRALIAS_EL1, bit [9]
When FEAT_SRMASK is implemented:

nCPACRALIAS_EL1, bit [8]
When FEAT_SRMASK is implemented:

nTCR2MASK_EL1, bit [7]
When FEAT_SRMASK is implemented:

nTCRMASK_EL1, bit [6]
When FEAT_SRMASK is implemented:

nSCTLR2MASK_EL1, bit [5]
When FEAT_SRMASK is implemented:

nSCTLRMASK_EL1, bit [4]
When FEAT_SRMASK is implemented:

nCPACRMASK_EL1, bit [3]
When FEAT_SRMASK is implemented:

nRCWSMASK_EL1, bit [2]
When FEAT_THE is implemented:

nERXGSR_EL1, bit [1]
When FEAT_RASv2 is implemented:

nPFAR_EL1, bit [0]
When FEAT_PFAR is implemented: