PMSCR_EL1

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PMSCR_EL1, Statistical Profiling Control Register (EL1)

Purpose

Configuration

This register is present only when FEAT_SPE is implemented. Otherwise, direct accesses to PMSCR_EL1 are UNDEFINED.

Attributes

Field descriptions

Bits [63:12]

EnVM, bit [11]
When FEAT_SPE_nVM is implemented and FEAT_NV is implemented:

Otherwise:

KE, bit [10]
When FEAT_SPE_EXC is implemented:

KE	Meaning
0b0	SPE Profiling exceptions taken to EL1 are always masked at EL1.
0b1	Enabled SPE Profiling exceptions taken to EL1 are masked at EL1 when PSTATE.PM is 1 and unmasked when PSTATE.PM is 0.

Otherwise:

EE, bits [9:8]
When FEAT_SPE_EXC is implemented:

Exception Enable.

EE	Meaning	Applies when
0b00	Disabled. SPE Profiling exceptions for EL1 are disabled. All of the following apply: Unless enabled by a higher Exception level, SPE Profiling exceptions are not generated. PMBSR_EL1.S drives the interrupt request signal PMBIRQ. Accesses to PMBSR_EL1 at EL1 ignore the value of HCR_EL2.NV1.
0b01	Reserved for software use in nested virtualization. Behaves as 0b00 for the purpose of controlling the SPE Profiling exception and interrupt request signal PMBIRQ, and as 0b11 for the purpose of accesses to PMBSR_EL1.	When FEAT_NV is implemented
0b10	Reserved for software use in nested virtualization. Behaves as 0b11 for the purposes of controlling the SPE Profiling exception and interrupt request signal PMBIRQ, and accesses to PMBSR_EL1.	When FEAT_NV is implemented
0b11	Enabled. SPE Profiling exceptions for EL1 are enabled, as follows: All Profiling Buffer management events are recorded in PMBSR_EL1, unless they are configured to be recorded in PMBSR_EL3 by MDCR_EL3.PMSEE or PMBSR_EL2 by PMSCR_EL2.EE. SPE Profiling exceptions are generated and taken to EL1 when unmasked and PMBSR_EL1.S is 1, unless the Effective value of HCR_EL2.TGE is 1, in which case the exception is taken to EL2. The interrupt request signal PMBIRQ is not asserted.

For more information on the values reserved for software use in nested virtualization, see PMSCR_EL2.EE.

If the Effective value of PMSCR_EL2.EE is 0b00, then the Effective value of PMSCR_EL1.EE is 0b00.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL1, this field resets to '00'.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Otherwise:

PCT, bits [7:6]
When EL2 is implemented:

Physical Timestamp. If timestamp sampling is enabled and the Profiling Buffer owning Exception level is EL1, requests which timestamp counter value is collected.

If FEAT_ECV is implemented, this is a two-bit field as shown. Otherwise, bit[7] is RES0.

PCT	Meaning	Applies when
0b00	Virtual timestamp. The collected timestamp is the physical counter minus the value of CNTVOFF_EL2.
0b01	Physical timestamp. The collected timestamp is the physical counter.
0b11	Guest physical timestamp. The collected timestamp is the physical counter minus a physical offset. If any of the following are true, the physical offset is zero, otherwise the physical offset is the value of CNTPOFF_EL2: SCR_EL3.ECVEn == 0. CNTHCTL_EL2.ECV == 0. FEAT_ECV_POFF is not implemented.	When FEAT_ECV is implemented

PCT

Meaning

Applies when

0b00

Virtual timestamp. The collected timestamp is the physical counter minus the value of CNTVOFF_EL2.

0b01

Physical timestamp. The collected timestamp is the physical counter.

0b11

Guest physical timestamp. The collected timestamp is the physical counter minus a physical offset. If any of the following are true, the physical offset is zero, otherwise the physical offset is the value of CNTPOFF_EL2:

SCR_EL3.ECVEn == 0.
CNTHCTL_EL2.ECV == 0.
FEAT_ECV_POFF is not implemented.

When FEAT_ECV is implemented

When EL2 is implemented, all of the following apply:

If the Profiling Buffer owning Exception level is EL1 and EL2 is enabled in the owning Security state, then the value of PMSCR_EL2.PCT might override or modify the meaning of this field.
If the Profiling Buffer owning Exception level is EL2, then this field is ignored by the PE.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

TS, bit [5]

PA, bit [4]

TS	Meaning
0b0	Timestamp packet recording disabled.
0b1	Timestamp packet recording enabled.

Physical Address sample enable.

PA	Meaning
0b0	Physical addresses are not collected.
0b1	Physical addresses are collected.

When EL2 is implemented, all of the following apply:

If the Profiling Buffer owning Exception level is EL1, then this field is combined with the Effective value PMSCR_EL2.PA to determine whether Physical addresses are collected.
If the Profiling Buffer owning Exception level is EL2, then this field is ignored by the PE.

For more information, see 'Controlling the data that is collected'.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

CX, bit [3]

CONTEXTIDR_EL1 sample enable. Enables recording of a Context packet containing the value of CONTEXTIDR_EL1.

CX	Meaning
0b0	CONTEXTIDR_EL1 recording disabled.
0b1	CONTEXTIDR_EL1 recording enabled.

The PE ignores the value of this field and CONTEXTIDR_EL1 is not recorded when any of the following apply:

The sampled operation executes at EL2.
The sampled operation executes at EL0 and the Effective value of HCR_EL2.TGE is 1.

For more information, see 'Controlling the data that is collected'.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Bit [2]

E1SPE, bit [1]

E0SPE, bit [0]

E1SPE	Meaning
0b0	Sampling disabled at EL1.
0b1	Sampling enabled at EL1.

E0SPE	Meaning
0b0	Sampling disabled at EL0.
0b1	Sampling enabled at EL0.

Accessing PMSCR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, PMSCR_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b1001	0b1001	0b000

if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().PMSCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x828); else X{64}(t) = PMSCR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = PMSCR_EL2(); else X{64}(t) = PMSCR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = PMSCR_EL1(); end;

MSR PMSCR_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b1001	0b1001	0b000

if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().PMSCR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPMS == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x828) = X{64}(t); else PMSCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then PMSCR_EL2() = X{64}(t); else PMSCR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then PMSCR_EL1() = X{64}(t); end;

When FEAT_VHE is implemented

MRS <Xt>, PMSCR_EL12

op0	op1	CRn	CRm	op2
0b11	0b101	0b1001	0b1001	0b000

if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x828); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = PMSCR_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = PMSCR_EL1(); else Undefined(); end; end;

When FEAT_VHE is implemented

MSR PMSCR_EL12, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b101	0b1001	0b1001	0b000

if !IsFeatureImplemented(FEAT_SPE) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x828) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && CheckMDCR_EL3_NSPBTrap() then Undefined(); elsif HaveEL(EL3) && CheckMDCR_EL3_NSPBTrap() then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else PMSCR_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then PMSCR_EL1() = X{64}(t); else Undefined(); end; end;

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RES0
RES0																				EnVM	KE	EE		PCT		TS	PA	CX	RES0	E1SPE	E0SPE

PMSCR_EL1, Statistical Profiling Control Register (EL1)

Purpose

Configuration

Attributes

Field descriptions

Bits [63:12]

EnVM, bit [11]When FEAT_SPE_nVM is implemented and FEAT_NV is implemented:

Otherwise:

KE, bit [10]When FEAT_SPE_EXC is implemented:

Otherwise:

EE, bits [9:8]When FEAT_SPE_EXC is implemented:

Otherwise:

PCT, bits [7:6]When EL2 is implemented:

Otherwise:

TS, bit [5]

PA, bit [4]

CX, bit [3]

Bit [2]

E1SPE, bit [1]

E0SPE, bit [0]

Accessing PMSCR_EL1

MRS <Xt>, PMSCR_EL1

MSR PMSCR_EL1, <Xt>

When FEAT_VHE is implemented

MRS <Xt>, PMSCR_EL12

When FEAT_VHE is implemented

MSR PMSCR_EL12, <Xt>

EnVM, bit [11]
When FEAT_SPE_nVM is implemented and FEAT_NV is implemented:

KE, bit [10]
When FEAT_SPE_EXC is implemented:

EE, bits [9:8]
When FEAT_SPE_EXC is implemented:

PCT, bits [7:6]
When EL2 is implemented: