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GICR_ISPENDR0

GICR_ISPENDR0, Interrupt Set-Pending Register 0

The GICR_ISPENDR0 characteristics are:

Purpose

Adds the pending state to the corresponding SGI or PPI.

Configuration

A copy of this register is provided for each Redistributor.

Attributes

GICR_ISPENDR0 is a 32-bit register.

Field descriptions

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Set_pending_bit31	Set_pending_bit30	Set_pending_bit29	Set_pending_bit28	Set_pending_bit27	Set_pending_bit26	Set_pending_bit25	Set_pending_bit24	Set_pending_bit23	Set_pending_bit22	Set_pending_bit21	Set_pending_bit20	Set_pending_bit19	Set_pending_bit18	Set_pending_bit17	Set_pending_bit16	Set_pending_bit15	Set_pending_bit14	Set_pending_bit13	Set_pending_bit12	Set_pending_bit11	Set_pending_bit10	Set_pending_bit9	Set_pending_bit8	Set_pending_bit7	Set_pending_bit6	Set_pending_bit5	Set_pending_bit4	Set_pending_bit3	Set_pending_bit2	Set_pending_bit1	Set_pending_bit0

Set_pending_bit<x>, bit [x], for x = 31 to 0

For PPIs and SGIs, adds the pending state to interrupt number x. Reads and writes have the following behavior:

Set_pending_bit<x>	Meaning
0b0	If read, indicates that the corresponding interrupt is not pending on this PE. If written, has no effect.
0b1	If read, indicates that the corresponding interrupt is pending, or active and pending on this PE. If written, changes the state of the corresponding interrupt from inactive to pending, or from active to active and pending. This has no effect in the following cases: If the interrupt is already pending because of a write to GICR_ISPENDR0. If the interrupt is already pending because the corresponding interrupt signal is asserted. In this case, the interrupt remains pending if the interrupt signal is deasserted.

Set_pending_bit<x>

Meaning

0b0

If read, indicates that the corresponding interrupt is not pending on this PE.

If written, has no effect.

0b1

If read, indicates that the corresponding interrupt is pending, or active and pending on this PE.

If written, changes the state of the corresponding interrupt from inactive to pending, or from active to active and pending. This has no effect in the following cases:

If the interrupt is already pending because of a write to GICR_ISPENDR0.
If the interrupt is already pending because the corresponding interrupt signal is asserted. In this case, the interrupt remains pending if the interrupt signal is deasserted.

The reset behavior of this field is:

On a GIC reset, this field resets to an architecturally UNKNOWN value.

Accessing GICR_ISPENDR0

When affinity routing is not enabled for the Security state of an interrupt in GICR_ISPENDR0, the corresponding bit is RAZ/WI and equivalent functionality is provided by GICD_ISPENDR<n> with n=0.

This register only applies to SGIs (bits [15:0]) and PPIs (bits [31:16]). For SPIs, this functionality is provided by GICD_ISPENDR<n>.

When GICD_CTLR.DS == 0, bits corresponding to Secure SGIs and PPIs are RAZ/WI to Non-secure accesses.

GICR_ISPENDR0 can be accessed through the memory-mapped interfaces:

Component	Frame	Offset	Instance
GIC Redistributor	SGI_base	0x0200	GICR_ISPENDR0

Accesses to this register are RW.

2026-03-26 20:27:25, 2026-03_rel