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MPAMCFG_CPBM<n>, MPAM Cache Portion Bitmap Partition Configuration Register, n = 0 - 1023

The MPAMCFG_CPBM<n> characteristics are:

Purpose

The MPAMCFG_CPBM<n> register array gives access to the cache portion bitmap. Each register in the array is a read/write register that configures the cache portions numbered from <n * 32> to <31 + (n * 32)> that a PARTID is allowed to allocate.

After setting MPAMCFG_PART_SEL with a PARTID, software writes to the MPAMCFG_CPBM<n> register to configure which cache portions the PARTID is allowed to allocate.

The MPAMCFG_CPBM<n> register that contains the bitmap bit corresponding to cache portion p has n equal to p[15:5]. The field, P<x>, of that MPAMCFG_CPBM<n> register that contains the bitmap bit corresponding to cache portion p has x equal to p[4:0].

Configuration

The power domain of MPAMCFG_CPBM<n> is IMPLEMENTATION DEFINED.

This register is present only when (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented) and MPAMF_IDR.HAS_CPOR_PART == '1'. Otherwise, direct accesses to MPAMCFG_CPBM<n> are RES0.

If MPAMF_IDR.HAS_RIS is 1, the control settings accessed are those of the resource instance currently selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

If FEAT_MPAMv0p1 or FEAT_MPAMv1p0 is implemented, the register is banked and the following statements apply:

• MPAMCFG_CPBM<n>_s controls the cache portions for the Secure PARTID selected by the Secure instance of MPAMCFG_PART_SEL.

• MPAMCFG_CPBM<n>_ns controls the cache portions for the Non-secure PARTID selected by the Non-secure instance of MPAMCFG_PART_SEL.

• If FEAT_RME is implemented, the following statements also apply:

  • MPAMCFG_CPBM<n>_rl controls the cache portions for the Realm PARTID selected by the Realm instance of MPAMCFG_PART_SEL.

  • MPAMCFG_CPBM<n>_rt controls the cache portions for the Root PARTID selected by the Root instance of MPAMCFG_PART_SEL.

The power and reset domain of each MSC component is specific to that component.

Attributes

MPAMCFG_CPBM<n> is a 32-bit register.

Field descriptions

P<x>, bit [x], for x = 31 to 0

Accessing MPAMCFG_CPBM<n>

If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply:

• In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:

• MPAMCFG_CPBM<n>_s must only be accessible from the Secure MPAM feature page.

• MPAMCFG_CPBM<n>_ns must only be accessible from the Non-secure MPAM feature page.

• MPAMCFG_CPBM<n>_rt must only be accessible from the Root MPAM feature page.

• MPAMCFG_CPBM<n>_rl must only be accessible from the Realm MPAM feature page.

• MPAMCFG_CPBM<n>_s, MPAMCFG_CPBM<n>_ns, MPAMCFG_CPBM<n>_rt, and MPAMCFG_CPBM<n>_rl must be separate registers:

• The Secure instance (MPAMCFG_CPBM<n>_s) accesses the cache portion bitmap used for Secure PARTIDs.

• The Non-secure instance (MPAMCFG_CPBM<n>_ns) accesses the cache portion bitmap used for Non-secure PARTIDs.

• The Root instance (MPAMCFG_CPBM<n>_rt) accesses the cache portion bitmap used for Root PARTIDs.

• The Realm instance (MPAMCFG_CPBM<n>_rl) accesses the cache portion bitmap used for Realm PARTIDs.

When RIS is implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the cache resource instance selected by MPAMCFG_PART_SEL.RIS and the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

When RIS is not implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL.

When PARTID narrowing is implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the internal PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 1.

When PARTID narrowing is not implemented, loads and stores to MPAMCFG_CPBM<n> access the cache portion bitmap configuration settings for the request PARTID selected by MPAMCFG_PART_SEL.PARTID_SEL, and MPAMCFG_PART_SEL.INTERNAL must be 0.

MPAMCFG_CPBM<n> can be accessed through the memory-mapped interfaces:

When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented, accesses to this register are RW.

When FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented, accesses to this register are RW.

When FEAT_RME is implemented and (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented), accesses to this register are RW.

When FEAT_RME is implemented and (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented), accesses to this register are RW.

2026-03-26 20:27:25, 2026-03_rel

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