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MPAMF_ECR, MPAM Error Control Register

The MPAMF_ECR characteristics are:

Purpose

MPAMF_ECR is a 32-bit read/write register that controls MPAM error interrupts for this MSC.

Configuration

The power domain of MPAMF_ECR is IMPLEMENTATION DEFINED.

This register is present only when FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented. Otherwise, direct accesses to MPAMF_ECR are RES0.

If FEAT_MPAMv1p0 or FEAT_MPAMv0p1 is implemented, then the following statements apply:

• MPAMF_ECR_s controls Secure MPAM error handling.

• MPAMF_ECR_ns controls Non-secure MPAM error handling.

• If FEAT_RME is implemented, then the following statements also apply:

  • MPAMF_ECR_rt controls Root MPAM error handling.

  • MPAMF_ECR_rl controls Realm MPAM error handling.

If an MSC cannot encounter any of the error conditions listed in MPAM MSC Errors of Arm® Memory System Resource Partitioning and Monitoring (MPAM) System Component Specification (ARM IHI 0099), both the MPAMF_ESR and MPAMF_ECR must be RAZ/WI.

The power and reset domain of each MSC component is specific to that component.

Attributes

MPAMF_ECR is a 32-bit register.

Field descriptions

Bits [31:1]

INTEN, bit [0]

Accessing MPAMF_ECR

If both FEAT_MPAM and FEAT_RME are implemented, the following statements apply:

• In a system that supports Secure, Non-secure, Root, and Realm memory maps, there must be MPAM feature pages in all four address maps:

• MPAMF_ECR_s must only be accessible from the Secure MPAM feature page.

• MPAMF_ECR_ns must only be accessible from the Non-secure MPAM feature page.

• MPAMF_ECR_rt must only be accessible from the Root MPAM feature page.

• MPAMF_ECR_rl must only be accessible from the Realm MPAM feature page.

• MPAMF_ECR_s, MPAMF_ECR_ns, MPAMF_ECR_rt, and MPAMF_ECR_rl must be separate registers:

• The Secure instance (MPAMF_ECR_s) accesses the error interrupt controls used for Secure PARTIDs.

• The Non-secure instance (MPAMF_ECR_ns) accesses the error interrupt controls used for Non-secure PARTIDs.

• The Root instance (MPAMF_ECR_rt) accesses the error interrupt controls used for Root PARTIDs.

• The Realm instance (MPAMF_ECR_rl) accesses the error interrupt controls used for Realm PARTIDs.

MPAMF_ECR can be accessed through the memory-mapped interfaces:

When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented, accesses to this register are RW.

When FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented, accesses to this register are RW.

When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented), accesses to this register are RW.

When FEAT_RME is implemented and (FEAT_MPAMv1p0 is implemented or FEAT_MPAMv0p1 is implemented), accesses to this register are RW.

2026-03-26 20:27:25, 2026-03_rel

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