PMZR_EL0

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PMZR_EL0, Performance Monitors Zero with Mask

Purpose

Configuration

External register PMZR_EL0 bits [63:0] are architecturally mapped to AArch64 System register PMZR_EL0[63:0].

This register is present only when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3p9 is implemented.

Attributes

Field descriptions

Bits [63:33]

F0, bit [32]
When FEAT_PMUv3_ICNTR is implemented:

Zero PMICNTR_EL0.

F0	Meaning
0b0	Write is ignored.
0b1	Set PMICNTR_EL0 to zero.

Accessing this field has the following behavior:

When SoftwareLockStatus(addrdesc), access to this field is RAZ/WI.
Otherwise, access to this field is WO/RAZ.

Otherwise:

C, bit [31]

Zero PMCCNTR_EL0.

C	Meaning
0b0	Write is ignored.
0b1	Set PMCCNTR_EL0 to zero.

Accessing this field has the following behavior:

When SoftwareLockStatus(addrdesc), access to this field is RAZ/WI.
Otherwise, access to this field is WO/RAZ.

P<m>, bit [m], for m = 30 to 0

Zero PMEVCNTR<m>_EL0.

P<m>	Meaning
0b0	Write is ignored.
0b1	Set PMEVCNTR<m>_EL0 to zero.

Accessing this field has the following behavior:

When m >= NUM_PMU_COUNTERS, access to this field is RAZ/WI.
Access to this field is RAZ/WI if all the following are true:
- FEAT_PMUv3_EXTPMN is implemented.
- m >= UInt(EffectiveEPMN()).
- !IsMostSecureAccess(addrdesc).
When SoftwareLockStatus(addrdesc), access to this field is RAZ/WI.
Otherwise, access to this field is WO/RAZ.

Accessing PMZR_EL0

When FEAT_PMUv3_EXT is implemented and FEAT_PMUv3p9 is not implemented, then this location might be used for PMSWINC_EL0. If PMSWINC_EL0 is not implemented, then accesses to this location are RES0.

Accesses to this register use the following encodings:

Accessible at offset 0xCA0 from PMU

When DoubleLockStatus(), or !IsCorePowered(), or !AllowExternalPMUAccess(addrdesc), accesses to this register generate an error response.
When (FEAT_PMUv3_EXTPMN is not implemented, or !IsMostSecureAccess(addrdesc), or PMCCR().OSLO == '0') and OSLockStatus(), accesses to this register generate an error response.
When SoftwareLockStatus(addrdesc), accesses to this register are WI.
Otherwise, accesses to this register are WO.

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																															F0
C	P30	P29	P28	P27	P26	P25	P24	P23	P22	P21	P20	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0

PMZR_EL0, Performance Monitors Zero with Mask

Purpose

Configuration

Attributes

Field descriptions

Bits [63:33]

F0, bit [32]When FEAT_PMUv3_ICNTR is implemented:

Otherwise:

C, bit [31]

P<m>, bit [m], for m = 30 to 0

Accessing PMZR_EL0

F0, bit [32]
When FEAT_PMUv3_ICNTR is implemented: