PMZR_EL0

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PMZR_EL0, Performance Monitors Zero with Mask

Purpose

Configuration

AArch64 System register PMZR_EL0 bits [63:0] are architecturally mapped to External register PMZR_EL0[63:0] when FEAT_PMUv3_EXT is implemented and FEAT_PMUv3p9 is implemented.

This register is present only when FEAT_PMUv3p9 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to PMZR_EL0 are UNDEFINED.

Attributes

Field descriptions

Bits [63:33]

F0, bit [32]
When FEAT_PMUv3_ICNTR is implemented:

Zero PMICNTR_EL0.

F0	Meaning
0b0	Write is ignored.
0b1	Set PMICNTR_EL0 to zero.

Accessing this field has the following behavior:

Access to this field is RAZ/WI if all the following are true:
- EL3 is implemented.
- PSTATE.EL != EL3.
- MDCR_EL3.EnPM2 == '0'.
Access to this field is RAZ/WI if all the following are true:
- EL0 is the current Exception level.
- PMUSERENR_EL0.UEN == '0' or PMUACR_EL1.F0 == '0'.
Access to this field is RAZ/WI if all the following are true:
- FEAT_FGT2 is implemented.
- EL2Enabled().
- PSTATE.EL IN {EL1, EL0}.
- HCR_EL2.[E2H,TGE] != '11'.
- (EL3 is implemented and SCR_EL3.FGTEn2 == '0') or HDFGWTR2_EL2.nPMICNTR_EL0 == '0'.
Access to this field is RAZ/WI if all the following are true:
- EL0 is the current Exception level.
- PMUSERENR_EL0.IR == '1'.
Otherwise, access to this field is WO/RAZ.

Otherwise:

C, bit [31]

Zero PMCCNTR_EL0.

C	Meaning
0b0	Write is ignored.
0b1	Set PMCCNTR_EL0 to zero.

Accessing this field has the following behavior:

Access to this field is RAZ/WI if all the following are true:
- FEAT_PMUv3p9 is implemented.
- EL0 is the current Exception level.
- PMUSERENR_EL0.UEN == '1'.
- PMUACR_EL1.C == '0'.
Access to this field is RAZ/WI if all the following are true:
- FEAT_PMUv3p9 is implemented.
- EL0 is the current Exception level.
- PMUSERENR_EL0.[UEN,CR] == '11'.
Otherwise, access to this field is WO/RAZ.

P<m>, bit [m], for m = 30 to 0

Zero PMEVCNTR<m>_EL0.

P<m>	Meaning
0b0	Write is ignored.
0b1	Set PMEVCNTR<m>_EL0 to zero.

Accessing this field has the following behavior:

When m >= GetNumEventCountersAccessible(), access to this field is RAZ/WI.
Access to this field is RAZ/WI if all the following are true:
- FEAT_PMUv3p9 is implemented.
- EL0 is the current Exception level.
- PMUSERENR_EL0.UEN == '1'.
- PMUACR_EL1.P<m> == '0'.
Access to this field is RAZ/WI if all the following are true:
- FEAT_PMUv3p9 is implemented.
- EL0 is the current Exception level.
- PMUSERENR_EL0.[UEN,ER] == '11'.
Otherwise, access to this field is WO/RAZ.

Accessing PMZR_EL0

Accesses to this register use the following encodings in the System register encoding space:

MSR PMZR_EL0, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b011	0b1001	0b1101	0b100

if !(IsFeatureImplemented(FEAT_PMUv3p9) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif PMUSERENR_EL0().EN == '0' && (!IsFeatureImplemented(FEAT_PMUv3p9) || PMUSERENR_EL0().UEN == '0') then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nPMZR_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ZeroPMUCounters(X{64}(t)); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nPMZR_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().TPM == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ZeroPMUCounters(X{64}(t)); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TPM == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TPM == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ZeroPMUCounters(X{64}(t)); end; elsif PSTATE.EL == EL3 then ZeroPMUCounters(X{64}(t)); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																															F0
C	P30	P29	P28	P27	P26	P25	P24	P23	P22	P21	P20	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0

PMZR_EL0, Performance Monitors Zero with Mask

Purpose

Configuration

Attributes

Field descriptions

Bits [63:33]

F0, bit [32]When FEAT_PMUv3_ICNTR is implemented:

Otherwise:

C, bit [31]

P<m>, bit [m], for m = 30 to 0

Accessing PMZR_EL0

MSR PMZR_EL0, <Xt>

F0, bit [32]
When FEAT_PMUv3_ICNTR is implemented: