ERRPIDR4

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ERRPIDR4, Peripheral Identification Register 4

Purpose

Configuration

Attributes

Field descriptions

Bits [31:8]

SIZE, bits [7:4]
When RAS System Architecture v2 is implemented:

Size of the component.

SIZE	Meaning
0b0000	FEAT_RASSA_4KB is implemented.
0b0010	FEAT_RASSA_16KB is implemented.
0b0100	FEAT_RASSA_64KB is implemented.

All other values are reserved.

Otherwise:

Size of the component.

SIZE	Meaning
0b0000	One of the following is true: The component uses a single 4KB block. The component uses an IMPLEMENTATION DEFINED number of 4KB blocks.
0b0001..0b1111	The component occupies 2^{ERRPIDR4.SIZE} 4KB blocks.

SIZE

Meaning

0b0000

One of the following is true:

The component uses a single 4KB block.
The component uses an IMPLEMENTATION DEFINED number of 4KB blocks.

0b0001..0b1111

The component occupies 2^{ERRPIDR4.SIZE} 4KB blocks.

DES_2, bits [3:0]

Designer, JEP106 continuation code.

The JEP106 identification and continuation codes are stored as follows:

ERRPIDR1.DES_0: JEP106 identification code bits[3:0].
ERRPIDR2.DES_1: JEP106 identification code bits[6:4].
ERRPIDR4.DES_2: JEP106 continuation code.

These codes indicate the designer of the component and not the implementer, except where the two are the same. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.

A JEP106 identification and continuation code takes the following form:

A sequence of zero or more numbers, all having the value 0x7F.
A following 8-bit number, that is not 0x7F, and where bit[7] is an odd parity bit.

The parity bit in the JEP106 identification code is not included.

Note

For example, Arm Limited is assigned the code 0x7F 0x7F 0x7F 0x7F 0x3B.

The continuation code is the number of times 0x7F appears before the final number. For example, a component designed by Arm Limited has the code 0x4.
The identification code is bits[6:0] of the final number. For example, a component designed by Arm Limited has the code 0x3B.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing ERRPIDR4

This section shows the offset of ERRPIDR4 when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRPIDR4.

ERRPIDR4 can be accessed through the memory-mapped interfaces:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								SIZE				DES_2