ERRPIDR1

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ERRPIDR1, Peripheral Identification Register 1

Purpose

Configuration

Attributes

Field descriptions

Bits [31:8]

DES_0, bits [7:4]

Designer, JEP106 identification code, bits [3:0].

The JEP106 identification and continuation codes are stored as follows:

ERRPIDR1.DES_0: JEP106 identification code bits[3:0].
ERRPIDR2.DES_1: JEP106 identification code bits[6:4].
ERRPIDR4.DES_2: JEP106 continuation code.

These codes indicate the designer of the component and not the implementer, except where the two are the same. To obtain a number, or to see the assignment of these codes, contact JEDEC http://www.jedec.org.

A JEP106 identification and continuation code takes the following form:

A sequence of zero or more numbers, all having the value 0x7F.
A following 8-bit number, that is not 0x7F, and where bit[7] is an odd parity bit.

The parity bit in the JEP106 identification code is not included.

Note

For example, Arm Limited is assigned the code 0x7F 0x7F 0x7F 0x7F 0x3B.

The continuation code is the number of times 0x7F appears before the final number. For example, a component designed by Arm Limited has the code 0x4.
The identification code is bits[6:0] of the final number. For example, a component designed by Arm Limited has the code 0x3B.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

PART_1, bits [3:0]

Part number, which is selected by the designer of the component and stored as follows:

For a component with a 12-bit part number:
- ERRPIDR1.PART_1 contains part number bits [11:8].
- ERRPIDR0.PART_0 contains part number bits [7:0].
For a component with a 16-bit part number:
- ERRPIDR1.PART_1 contains part number bits [15:12].
- ERRPIDR0.PART_0 contains part number bits [11:4].
- ERRPIDR2.REVISION contains part number bits [3:0].

When a 12-bit part number is used, ERRPIDR2.REVISION indicates revision information.

The choice of using a 12-bit part number or 16-bit part number is specific to the designer of the component.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing ERRPIDR1

This section shows the offset of ERRPIDR1 when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRPIDR1.

ERRPIDR1 can be accessed through the memory-mapped interfaces:

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								DES_0				PART_1