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TRBPIDR0, Peripheral Identification Register 0

The TRBPIDR0 characteristics are:

Purpose

Provides discovery information about the component.

For additional information, see the CoreSight Architecture Specification.

Configuration

TRBPIDR0 is in the Core power domain.

This register is present only when FEAT_TRBE_EXT is implemented. Otherwise, direct accesses to TRBPIDR0 are RES0.

Attributes

TRBPIDR0 is a 32-bit register.

Field descriptions

Bits [31:8]

PART_0, bits [7:0]

Accessing TRBPIDR0

TRBPIDR0 can be accessed through the external debug interface:

Accessible as follows:

• When DoubleLockStatus() or !IsCorePowered(), accesses to this register generate an error response.
• Otherwise, accesses to this register are RO.

2026-03-26 20:27:25, 2026-03_rel

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